Conventionally, a shift register is configured to determine whether to output an enabled gate driving signal according to an internal control signal and maintain the gate driving signal and the control signal in a low-voltage level while in a period of no need to output an enabled gate driving signal, thereby preventing the shift register from outputting the enabled gate driving signal to mistakenly drive the respective gate lines. Thus, it is an important subject for a shift register to quickly pull down the gate driving signal and the control signal to a low-voltage level and stably maintain the gate driving signal and the control signal in the low-voltage level while there is no need to output an enabled gate driving signal.